The present invention relates generally to integrated circuit packaging and, more particularly, to system-in-package (SiP) packaging for minimizing bond wire contamination and yield loss.
As portable electronic devices become smaller, the dimensions of semiconductor packages in the electronic devices must also be reduced. To help accomplish this, system-in-package technology is widely used because it can increase the capacity of the semiconductor package. SiP packages include a plurality of chips, which are stacked and may be connected to each other by way of solder bumps and/or wire bonding.
FIG. 1. is a cross-sectional view of a conventional flip chip-based SiP package having bond wires. Package 10 comprises a substrate 20 having first and second surfaces 30 and 40, respectively. A plurality of solder balls 110 are disposed on the first surface 30. A plurality of solder bumps 60 electrically connect the second surface 40 of the substrate 20 to an active surface of a large chip 50, such as for example a digital device. A small chip 80, such as an analog device, is stacked on a back surface of the large chip 50. Bond wires 90 electrically couple the small chip 80 to bond pads 95 on substrate 20.
To provide mechanical reinforcement to the large chip 50 and the substrate 20, an underfill material 70, such as resin, is typically dispensed in the gap between the large chip 50 and the substrate 20. This gap, if not underfilled, would easily cause the package 10 to suffer from fatigue cracking and electrical failure when it is being subjected to high-temperature conditions. One drawback to conventional underfill processes, however is that prior to the wire bonding process, the dispensed resin would easily flow wayward to nearby bond pads, contaminating them and making proper wire bonding of bond wires 90 to bond pads 95 difficult, if not impossible, resulting in yield loss. For this reason, chip package designers typically specify that a minimum distance A between an edge of the large chip 50 and the bond pad 95 of the substrate be more than 0.3 mm to avoid the underfill material overflowing the bond pads. However, due to this design rule constraint, designers are often not afforded design flexibility, which exacerbates the situation because they are precluded from manufacturing packages having reduced dimensions.
FIG. 1 shows a cross-sectional view of a SiP package where the underfill material 70 does not overflow on a bond pad 95. FIGS. 2A and 2B show examples of SiP packages depicting the overflow problem 120. FIG. 2A shows underfill material 70 overflowing a bond pad 95 in a flip chip-based SiP package; whereas FIG. 2B shows an adhesive material 75 overflowing a bond pad 95 in a wire bond SiP package.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved SiP package for minimizing bond wire contamination and yield loss and a method thereof that avoids the reliability concerns associate with conventional SiP packages.